1. Field of the Invention
The present invention relates to a signal resynchronization apparatus for use in digital communications equipment, and more particularly, to a signal resynchronization apparatus for receiving an incoming data stream in synchronization with a first clock and outputting the same data stream in synchronization with a second clock.
2. Description of the Related Art
In some types of digital communications equipment, signals are received and transmitted with different clock timings. This means that the incoming signal is entered in synchronization with a reception clock (first clock), processed in the equipment, and then retransmitted in synchronization with a transmission clock (second clock). While having the same average frequencies, the first and second clocks are not always in phase. This kind of signal resynchronization is usually accomplished by using, for example, a dual port memory device that functions as first-in first-out (FIFO) buffer storage, as well as allowing write and read operations to be performed independently.
The following section will describe a conventional signal resynchronization apparatus with reference to its block diagram of FIG. 11. As FIG. 11 illustrates, this conventional apparatus comprises a memory 10, a write address generator 11, a phase monitor 12, and a read address generator 13. The memory 10 comprises a dual port RAM having two separate ports to allow simultaneous read and write operations of, for example, 8-bit wide parallel data. FIG. 12 shows the notation of address and data of the memory 10. The memory 10 has N-byte storage cells being addressed from 1 to N (N: an integer number). The write address generator 11 produces write address signals, from 1 to N, in synchronization with a reception clock (first clock). On the other hand, the read address generator 13 generates read address signals, from 1 to N, in synchronization with a transmission clock (second clock).
When the illustrated apparatus is powered up, a power-on reset signal is generated for system initialization purposes. Upon receipt of this power-on reset signal, the phase monitor 12 produces, a control signal to suppress the operation of the read address generator 13 until the difference between the write address and read address reaches a predetermined address distance (or phase difference).
The operation of this conventional signal resynchronization apparatus will now be described below with reference to FIG. 13.
The write address generator 11 produces write address signals in synchronization with the first clock and supplies them to the memory 10 to drive its data input port. The memory 10 accepts write data and stores it into one of its storage cell addressed by the write address signals supplied from the write address generator 11. For example, FIG. 13 shows that an incoming data word xe2x80x9cdata1xe2x80x9d is written into ADDRESS:1, when the write address has a value of xe2x80x9c1.xe2x80x9d
Independently of the above data write operation, the read address generator 13 produces read address signals in synchronization with the second clock and supplies them to the memory 10 to drive its data output port. The memory 10 selects one of its storage cells with the read address signals provided by the read address generator 13 and reads out its contents. For example, a data word xe2x80x9cdataXxe2x80x9d is read out from ADDRESS:X when the read address has a value of xe2x80x9cX,xe2x80x9d as shown in FIG. 13.
The write and read addresses produced by the write and read address generators 11 and 13 are such a circular address that increases from 1 to N and returns to 1 after reaching N. In other words, there are two independent address pointers to write and read the memory 10 as illustrated in FIG. 13. The write address pointer and read address pointer will cyclically scan the memory 10 while, ideally, keeping a predetermined distance from each other.
FIG. 14 shows a problem situation where the write address pointer has happened to catch up with the read address pointer because of a variation in incoming data timings or the like. In this situation, a write operation can be attempted to the same memory address where a read operation is being effected concurrently. This address pointer overlap would corrupt the read data, and the corrupted data could affect the operation of other part of the system. Particularly when the corrupted data is critical to the system, as in the case of K1/K2 bits for Automatic Protection Switch (APS) functions in the Synchronous Optical Network (SONET) architecture, the data corruption could disrupt the entire system.
Another problem situation may occur when the signal resynchronization apparatus is operating with a small distance (small phase difference) between the write and read address pointers. In such a situation, power supply fluctuations and/or ambient temperature variations would influence the phase difference between the two pointers, and as a result, the apparatus could experience frequent read data corruption. What is worse is that it is often hard to isolate and locate a problem, when it is caused by voltage or temperature variations.
The factors of data corruption problems are not limited within the inside, but can also be observed outside the signal resynchronization apparatus. A break in wiring, for example, will interrupt the incoming data stream and thus cause a corruption of a data word that is to be written into the memory 10. When this happened to some critical data of the system unfortunately, the problem would exert a serious influence on the entire system operation.
Taking the above into consideration, an object of the present invention is to provide a signal resynchronization apparatus which avoids read data corruption.
Particularly, the present invention aims to provide a signal resynchronization apparatus which avoids the corruption of such critical data that may affect the entire system operation.
To accomplish the above objects, according to the present invention, there is provided a signal resynchronization apparatus which receives a data stream in synchronization with a first clock and outputs the data stream in synchronization with a second clock, where the data stream contains a plurality of data words having an N-byte cyclic data structure. This apparatus comprises the following elements: (a) an input unit which receives the data stream from an external source; (b) a storage unit, having a capacity of at least (Mxc3x97N) bytes (M=2, 3, 4, . . . ), which stores the data stream received by the input unit; (c) a data writing unit, having a write address pointer, which sequentially writes each data word of the received data stream into the storage unit in synchronization with the first clock; (d) a data reading unit, having a read address pointer, which sequentially reads out each data word from the storage unit in synchronization with the second clock; (e) an output unit which outputs to an external destination the data words read out by the data reading unit; (f) a detection unit which detects that the write and read address pointers have come within a predetermined threshold distance; and (g) a relocation unit which moves the read address pointer by (Pxc3x97N) bytes (P=1, 2, 3, . . . ) to increase the distance between the read and write address pointers, when the detection unit has detected that the write and read address pointers have come within the predetermined threshold distance.
Further, to accomplish the above objects, according to the present invention, there is provided a signal resynchronization apparatus which receives a data stream in synchronization with a first clock and outputs the data stream in synchronization with a second clock, where the data stream contains a plurality of data words having an N-byte cyclic data structure. This apparatus comprises the following elements: (a) an input unit which receives the data stream from an external source; (b) a storage unit which stores the data stream received by the input unit; (c) a decision data generator which generates decision data that is used to determine whether the received data stream is correct; (d) an insertion unit which inserts the decision data generated by the decision data generator into the N-byte data stream received by the input unit; (e) a data writing unit, having a write address pointer, which sequentially writes each data word of the N-byte data stream with the decision data into the storage unit in synchronization with the first clock; (f) a data reading unit, having a read address pointer, which sequentially reads out each data word of the N-byte data stream from the storage unit in synchronization with the second clock; and (g) a decision unit which tests whether the data words read out by the data reading unit are correct, referring to the decision data inserted therein.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.